The present invention relates to a charge transfer device and its driving method, and more particularly to a charge transfer device driven by a low voltage.
Conventional charge transfer devices now on the market are driven by a DC supply voltage from 12 to 15 V and the transfer pulse voltage lies from 5 to 12 V in general. However, when taking into account the overall system configuration using charge transfer devices, since almost all the semiconductor devices are usually driven by 5 V, it is preferable to realize a charge transfer device (CTD) whose DC supply voltage and transfer pulse voltage for charge coupled device (CCD) registers are both 5 V (referred to as complete 5 V CTDs).
With respect to the realization of 5 V transfer pulse CTDs, since a potential difference (barrier height) between the barrier portion and the storage portion to both of which an in-phase transfer pulse is applied, can be optimized within a conventional controllable range on the basis the two-phase driving method now widely adopted as the charge transfer device driving technique, it is possible to realize satisfactory 5 V transfer pulse CTDs even if the potential difference margin is reduced during transfer operation.
With respect to the realization of 5 V DC supply voltage CTDs, the problem is how to minimize the voltage applied to the reset drains for detecting and discharging charges transferred to the output portion. Various techniques have been so far proposed with respect to the above-mentioned minimization of the reset drain voltage.
The first method is to obtain a high reset drain voltage on the basis of an internal voltage boosting circuit.
That is, a high voltage is generated internally by use of a 5 V supply voltage and a 5 V pulse voltage both supplied from outside and the generated high voltage is applied to the reset drains. In this method, however, there exist problems in that a relatively-large area is required to form such a voltage generating circuit as described above, and additionally the signal S/N ratio is reduced because the generated high voltage is subjected to the influence of noise and therefore noise is superposed upon the output signal.
The second method is to directly supply an external DC supply voltage to the reset drains from outside. The typical methods are disclosed in U.S. Pat. No. 4,603,426 or in Japanese Patent Application No. 63-77676 (Japanese Patent Laid-open (Kokai) No. 1-248664) proposed by the same inventor. In more detail, U.S. Pat. No. 4,603,426 discloses such a method that the final stage is driven by a voltage from -4 to 5 V and the other stages are driven by a transfer clock pulse changing from 0 to 5 V. Japanese Patent Appli. No. 63-77676 discloses such a method where the final stage is driven by a clock pulse changing between a -3 V or less low-voltage level and a 5 V or more high-voltage level and the other stages are driven by a transfer clock pulse changing from 0 to 5 V. Further, a 5 V supply voltage is directly supplied to the reset drains in both the above-mentioned second conventional methods.
In the prior art CCD registers as described above, however, since the final transfer stage is driven by a clock pulse whose amplitude is wider than that of the externally-applied clock pulse, there exists a problem in that induced noise is easily superposed upon the CCD output signal and therefore the S/N ratio is deteriorated. Further, there exists another problem in that an additional circuit for increasing the clock pulse amplitude requires as large an area as possible for the high voltage generating circuit explained in the first conventional method.